Description 

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the ‘7490A and ’74LS90, divide-by-six for the ‘7492A and ’74LS92, and the divide-by eight for the ‘7493A and ’74LS93. All of these counters have a gated zero reset and the ’90A and ‘LS90 also have gated set-to-nine inputs for use in BCD nine’s complement applications.

Pinout

Features

To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the Q_A output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the ‘7490A or ’74LS90 counters by connecting the Q_D output to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output Q_A .

• ’90A, ‘LS90 . . . Decade Counters ( SN74LS90N )
• ’92A, ‘LS92 . . . Divide By-Twelve Counters
• ’93A, ‘LS93 . . . 4-Bit Binary Counters

SN74LS90N Datasheet PDF Download